1. Field of the Invention
The present invention relates to a signal transmission system and a receiver circuit for use in the signal transmission system, and more particularly, to a signal transmission system for transmitting signals between LSI chips and a receiver circuit for use in the same.
2. Description of the Related Art
Recently, DRAM (Dynamic Random Access Memory) and processor performances have improved dramatically, and more specifically, processor performance has improved rapidly in terms of speed, while the improvement of DRAM performance has been dramatic primarily in terms of storage capacity. However, the improvement in operating speed of DRAM has not been so dramatic as the increase in storage capacity, as a result of which the speed gap between DRAM and processor has widened and this speed gap has become a bottleneck in boosting computer performance in recent years.
Among the signal transmission systems for signal transmission between processors and DRAMs (DRAM modules) known in the prior art and expected to find widespread use in the next few years are the SSTL (Series-Stub Terminated Logic) and other low-amplitude signaling standards. In the SSTL (or in a similar low-amplitude signaling system), a signal transmission line (hereinafter the transmission line) is terminated in a resistance close to the characteristic impedance of the transmission line, thereby suppressing reflections at its terminating ends and achieving high signal transmission speeds. Furthermore, by using low-amplitude signaling, the power required to charge and discharge the transmission line is reduced, making low-power transmission possible in high-speed operation.
In a bus system (signal transmission system) employing the SSTL, high-speed signal transmission is made possible because of matched termination (terminal resistance) and stub resistance, and power consumption also is reduced compared to traditional systems because of the use of low-amplitude signaling. However, in order to maintain the overall power consumption of the apparatus at the current level, or reduce it below the current level, while increasing the signal transmission bandwidth between DRAM and processor, a signal transmission system with lower power consumption is demanded.
Further, for example, in a Rambus channel, a DRAM controller and a plurality of DRAM chips are interconnected by a common signal transmission line (bus). For transmission and reception of high-speed signals, precise timing must be established between the signal sender and receiver. In the Rambus channel, correct timing can be established for both reception and transmission, provided that a clock line and a signal transmission line are identical both in routing and in electrical characteristics. That is, the Rambus channel requires that the clock line and the signal transmission line be formed along the same route and have the same electrical characteristics between them.
However, the characteristic of the load is inevitably different between the clock line and the signal transmission line. This is because, while the signal transmission line permits the use of a latch circuit operating in synchronism with receive timing to achieve high-sensitivity reception, the clock line requires the use of a differential amplifier, etc. since a latch cannot be used. Since the nature of the load is different between a latch circuit and a differential amplifier and the like, line electrical characteristics (for example, delay per unit distance), etc. are bound to become different between the clock line and the signal transmission line.
The prior and related arts, and their associated problems will be described in detailed later with reference to the accompanying drawings